Wire sizing, repeater insertion and dominant time constant optimizationfor a bus line 2004 = Tamaño de cable, inserción de repetidores y optimización del tiempo dominante constante para una línea digital de un bus

CONTENIDO DE LIBRE ACCESO

Este contenido es de libre acceso. Solo haz clic en el siguiente botón.

Descripción: Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cables are needed, this scaling comes along with power increase and undesired cross talk effects between the wires which might affect the signal itself. A trade-off curve between power, area and delay is required so that a tuned solution for a specific problem might be found. Here, an approach based on the dominant time constant optimization technique for modelling of the delay is investigated for an initial square topology with uniform wire and repeater sizing based on convex optimization and Linear Matrix Inequalities. Results with optimal buffer insertion across the bus are also investigated.
Citación recomendada (normas APA)
: David Leonardo Moreno Bedoya, "Wire sizing, repeater insertion and dominant time constant optimizationfor a bus line 2004 = Tamaño de cable, inserción de repetidores y optimización del tiempo dominante constante para una línea digital de un bus", -:-, 2004. Consultado en línea en la Biblioteca Digital de Bogotá (https://www.bibliotecadigitaldebogota.gov.co/resources/2081102/), el día 2025-05-01.